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1 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read july 2000 ?2000 fairchild semiconductor international fm93cs46 (microwire? bus interface) 1024-bit serial eeprom with data protect and sequential read general description fm93cs46 is a 1024-bit cmos non-volatile eeprom organized as 64 x 16-bit array. this device features microwire interface which is a 4-wire serial bus with chipselect (cs), clock (sk), data input (di) and data output (do) signals. this interface is compat- ible to many of standard microcontrollers and microprocessors. fm93cs46 offers programmable write protection to the memory array using a special register called protect register. selected memory locations can be protected against write by programming this protect register with the address of the first memory location to be protected (all locations greater than or equal to this first address are then protected from further change). additionally, this address can be ?ermanently locked?into the device, making all future attempts to change data impossible. in addition this device features ?equential read? by which, entire memory can be read in one cycle instead of multiple single byte read cycles. there are 10 instructions implemented on the fm93cs46, 5 of which are for memory operations and the remaining 5 are for protect register operations. this device is fabricated using fairchild semiconduc- tor floating-gate cmos process for high reliability, high endurance and low power consumption. ?z?and ??versions of fm93cs46 offer very low standby current making them suitable for low power applications. this device is offered in both so and tssop packages for small space considerations. functional diagram features wide v cc 2.7v - 5.5v programmable write protection sequential register read typical active current of 200 a 10 a standby current typical 1 a standby current typical (l) 0.1 a standby current typical (lz) no erase instruction required before write instruction self timed write cycle device status during programming cycles 40 year data retention endurance: 1,000,000 data changes packages available: 8-pin so, 8-pin dip, 8-pin tssop instruction decoder control logic and clock generators comparator and write enable high voltage generator and program timer instruction register address register protect register eeprom array read/write amps data in/out register 16 bits decoder 16 16 data out buffer pre pe cs sk di do v ss v cc
2 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read connection diagram dual-in-line package (n) 8Cpin so (m8) and 8Cpin tssop (mt8) top view package number n08e, m08a and mtc08 pin names cs chip select sk serial data clock di serial data input do serial data output gnd ground pe program enable pre protect register enable v cc power supply ordering information fm 93 cs xx t lz e xxx letter description package n 8-pin dip m8 8-pin so mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current blank normal pin out t rotated pin out density 46 1024 bits c cmos cs data protect and sequential read interface 93 microwire fairchild memory prefix v cc pe gnd cs sk di do 1 2 3 4 8 7 6 5 pre pe do di pre v cc cs sk 1 2 3 4 8 7 6 5 gnd normal pinout rotated pinout
3 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature fm93cs46 0 c to +70 c fm93cs46e -40 c to +85 c fm93cs46v -40 c to +125 c power supply (v cc ) 4.5v to 5.5v dc and ac electrical characteristics v cc = 4.5v to 5.5v unless otherwise specified symbolparameter conditions min max units i cca operating current cs = v ih , sk=1.0 mhz 1 ma i ccs standby current cs = v il 50 a i il input leakage v in = 0v to v cc -1 a i ol output leakage (note 2) v il input low voltage -0.1 0.8 v v ih input high voltage 2 v cc +1 v ol1 output low voltage i ol = 2.1 ma 0.4 v v oh1 output high voltage i oh = -400 a 2.4 v ol2 output low voltage i ol = 10 a 0.2 v v oh2 output high voltage i oh = -10 av cc - 0.2 f sk sk clock frequency (note 3) 1 mhz t skh sk high time 0 c to +70 c 250 ns -40 c to +125 c 300 t skl sk low time 250 ns t cs minimum cs low time (note 4) 250 ns t css cs setup time 50 ns t pres pre setup time 50 ns t dh do hold time 70 ns t pes pe setup time 50 ns t dis di setup time 100 ns t csh cs hold time 0 ns t peh pe hold time 250 ns t preh pre hold time 50 ns t dih di hold time 20 ns t pd output delay 500 ns t sv cs to status valid 500 ns t df cs to do in hi-z cs = v il 100 ns t wp write cycle time 10 ms
4 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read absolute maximum ratings (note 1) ambient storage temperature -65 c to +150 c all input or output voltages +6.5v to -0.3v with respect to ground lead temperature (soldering, 10 sec.) +300 c esd rating 2000v operating conditions ambient operating temperature fm93cs46l/lz 0 c to +70 c fm93cs46le/lze -40 c to +85 c fm93cs46lv/lzv -40 c to +125 c power supply (v cc ) 2.7v to 5.5v dc and ac electrical characteristics v cc = 2.7v to 4.5v unless otherwise specified. refer to page 3 for v cc = 4.5v to 5.5v. symbolparameter conditions min max units i cca operating current cs = v ih , sk=256 khz 1 ma i ccs standby current cs = v il l 10 a lz (2.7v to 4.5v) 1 a i il input leakage v in = 0v to v cc 1 a i ol output leakage (note 2) v il input low voltage -0.1 0.15v cc v v ih input high voltage 0.8v cc v cc +1 v ol output low voltage i ol = 10 a 0.1v cc v v oh output high voltage i oh = -10 a 0.9v cc f sk sk clock frequency (note 3) 0 250 khz t skh sk high time 1 s t skl sk low time 1 s t cs minimum cs low time (note 4) 1 s t css cs setup time 0.2 s t pres pre setup time 50 ns t dh do hold time 70 ns t pes pe setup time 50 ns t dis di setup time 0.4 s t csh cs hold time 0 ns t peh pe hold time 250 ns t preh pre hold time 50 ns t dih di hold time 0.4 s t pd output delay 2 s t sv cs to status valid 1 s t df cs to do in hi-z cs = v il 0.4 s t wp write cycle time 15 ms capacitance t a = 25 c, f = 1 mhz or 256 khz (note 5) symboltest typ max units c out output capacitance 5 pf c in input capacitance 5 pf note 1 : stress above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2 : typical leakage values are in the 20na range. note 3 : the shortest allowable sk clock period = 1/f sk (as shown under the f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/f sk = t skhminimum + t sklminimum for shorter sk cycle time operation. note 4 : cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagram on the following page.) note 5 : this parameter is periodically sampled and not 100% tested. ac test conditions v cc range v il /v ih v il /v ih v ol /v oh i ol /i oh input levels timing level timing level 2.7v v cc 5.5v 0.3v/1.8v 1.0v 0.8v/1.5v 10 a (extended voltage levels) 4.5v v cc 5.5v 0.4v/2.4v 1.0v/2.0v 0.4v/2.4v 2.1ma/-0.4ma (ttl levels) output load: 1 ttl gate (c l = 100 pf)
5 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read pin description chip select (cs) this is an active high input pin to fm93cs46 eeprom (the device) and is generated by a master that is controlling the device. a high level on this pin selects the device and a low level deselects the device. all serial communications with the device is enabled only when this pin is held high. however this pin cannot be permanently tied high, as a rising edge on this signal is required to reset the internal state-machine to accept a new cycle and a falling edge to initiate an internal programming after a write cycle. all activity on the sk, di and do pins are ignored while cs is held low. serial clock (sk) this is an input pin to the device and is generated by the master that is controlling the device. this is a clock signal that synchronizes the communication between a master and the device. all input informa- tion (di) to the device is latched on the rising edge of this clock input, while output data (do) from the device is driven from the rising edge of this clock input. this pin is gated by cs signal. serial input (di) this is an input pin to the device and is generated by the master that is controlling the device. the master transfers input informa- tion (start bit, opcode bits, array addresses and data) serially via this pin into the device. this input information is latched on the rising edge of the sck. this pin is gated by cs signal. serial output (do) this is an output pin from the device and is used to transfer output data via this pin to the controlling master. output data is serially shifted out on this pin from the rising edge of the sck. this pin is active only when the device is selected. protect register enable (pre) this is an active high input pin to the device and is used to distinguish operations to memory array and operations to protect register. when this pin is held low, operations to the memory array are enabled. when this pin is held high, operations to the protect register are enabled. this pin operates in conjunction with pe pin. refer table1 for functional matrix of this pin for various operations. program enable (pe) this is an active high input pin to the device and is used to enable operations, that are write in nature, to the memory array and to the protect register. when this pin is held high, operations that are write in nature are enabled. when this pin is held low, operations that are write in nature are disabled. this pin operates in conjunction with pre pin. refer table1 for functional matrix of this pin for various operations. microwire interface a typical communication on the microwire bus is made through the cs, sk, di and do signals. to facilitate various operations on the memory array and on the protect register, a set of 10 instructions are implemented on fm93cs46. the format of each instruction is listed in table 1. instruction each of the above 10 instructions is explained under individual instruction descriptions. start bit this is a 1-bit field and is the first bit that is clocked into the device when a microwire cycle starts. this bit has to be 1 for a valid cycle to begin. any number of preceding 0 can be clocked into the device before clocking a 1 . opcode this is a 2-bit field and should immediately follow the start bit. these two bits (along with pre, pe signals and 2 msb of address field) select a particular instruction to be executed. address field this is a 6-bit field and should immediately follow the opcode bits. in fm93cs46, all 6 bits are used for address decoding during read, write and prwrite instructions. during all other in- structions (with the exception of prread), the msb 2 bits are used to decode instruction (along with opcode bits, pre and pe signals). data field this is a 16-bit field and should immediately follow the address bits. only the write and wrall instructions require this field. d15 (msb) is clocked first and d0 (lsb) is clocked last (both during writes as well as reads). table 1. instruction set instruction start bit opcode field address field data field pre pin pe pin read 1 10 a5 a4 a3 a2 a1 a0 0 x wen 1 00 1 1xxxx 0 1 write 1 01 a5 a4 a3 a2 a1 a0 d15-d0 0 1 wrall 1 00 0 1 xxxx d15-d0 0 1 wds 1 00 0 0xxxx 0 x prread 1 10 x x xxxx 1 x pren 1 00 1 1 xxxx 1 1 prclear 1 11 111111 1 1 prwrite 1 01 a5 a4 a3 a2 a1 a0 1 1 prds 1 00 000000 1 1
6 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read functional description a typical microwire cycle starts by first selecting the device (bringing the cs signal high). once the device is selected, a valid start bit ( 1 ) should be issued to properly recognize the cycle. following this, the 2-bit opcode of appropriate instruction should be issued. after the opcode bits, the 6-bit address information should be issued. for certain instructions, some (or all) of these 6 bits are don t care values (can be 0 or 1 ), but they should still be issued. following the address information, depending on the instruction (write and wrall), 16-bit data is issued. other- wise, depending on the instruction (read and prread), the device starts to drive the output data on the do line. other instructions perform certain control functions and do not deal with data bits. the microwire cycle ends when the cs signal is brought low. however during certain instructions, falling edge of the cs signal initiates an internal cycle (programming), and the device remains busy till the completion of the internal cycle. each of the 10 instructions is explained in detail in the following sections. memory instructions following five instructions, read, wen, write, wrall and wds are specific to operations intended for memory array. the pre pin should be held low during these instructions. 1) read and sequential read (read) read instruction allows data to be read from a selected location in the memory array. input information (start bit, opcode and address) for this instruction should be issued as listed under table1. upon receiving a valid input information, decoding of the opcode and the address is made, followed by data transfer from the selected memory location into a 16-bit serial-out shift register. this 16-bit data is then shifted out on the do pin. d15 bit (msb) is shifted out first and d0 bit (lsb) is shifted out last. a dummy-bit (logical 0) precedes this 16-bit data output string. output data changes are initiated on the rising edge of the sk clock. after reading the 16-bit data, the cs signal can be brought low to end the read cycle. the pre pin should be held low during this cycle. refer read cycle diagram . this device also offers sequential memory read operation to allow reading of data from the additional memory locations instead of just one location. it is started in the same manner as normal read but the cycle is continued to read further data (instead of terminat- ing after reading the first 16-bit data). after providing 16-bit data, the device automatically increments the address pointer to the next location and continues to provide the data from that location. any number of locations can be read out in this manner, however, after reading out from the last location, the address pointer points back to the first location. if the cycle is continued further, data will be read from this first location onward. in this mode of read, the dummy-bit is present only when the very first data is read (like normal read cycle) and is not present on subsequent data reads. the pre pin should be held low during this cycle. refer sequen- tial read cycle diagram . 2) write enable (wen) when v cc is applied to the part, it powers up in the write disable (wds) state. therefore, all programming operations (for both memory array and protect register) must be preceded by a write enable (wen) instruction. once a write enable instruction is executed, programming remains enabled until a write disable (wds) instruction is executed or v cc is completely removed from the part. input information (start bit, opcode and address) for this wen instruction should be issued as listed under table1. the device becomes write-enabled at the end of this cycle when the cs signal is brought low. the pre pin should be held low during this cycle. execution of a read instruction is independent of wen instruction. refer write enable cycle diagram. 3) write (write) write instruction allows write operation to a specified location in the memory with a specified data. this instruction is valid only when the following are true: device is write-enabled (refer wen instruction) address of the write location is not write-protected pe pin is held high during this cycle pre pin should be held low during this cycle input information (start bit, opcode, address and data) for this write instruction should be issued as listed under table1. after inputting the last bit of data (d0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. the status of the internal programming cycle can be polled at any time by bringing the cs signal high again, after t cs interval. when cs signal is high, the do pin indicates the ready/busy status of the chip. do = logical 0 indicates that the programming is still in progress. do = logical 1 indicates that the programming is finished and the device is ready for another instruction. it is not required to provide the sk clock during this status polling. while the device is busy, it is recommended that no new instruction be issued. refer write cycle diagram. it is also recommended to follow this instruction (after the device becomes ready) with a write disable (wds) instruction to safeguard data against corruption due to spurious noise, inadvert- ent writes etc. 4) write all (wrall) write all (wrall) instruction is similar to the write instruction except that wrall instruction will simultaneously program all memory locations with the data pattern specified in the instruction. this instruction is valid only when the following are true: protect register has been cleared (refer prclear instruction) device is write-enabled (refer wen instruction) pe pin is held high during this cycle pre pin should be held low during this cycle input information (start bit, opcode, address and data) for this wrall instruction should be issued as listed under table1. after inputting the last bit of data (d0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer write all cycle diagram.
7 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read 5) write disable (wds) write disable (wds) instruction disables all programming opera- tions and is recommended to follow all programming operations. executing this instruction after a valid write instruction would protect against accidental data disturb due to spurious noise, glitches, inadvertent writes etc. input information (start bit, opcode and address) for this wds instruction should be issued as listed under table1. the device becomes write-disabled at the end of this cycle when the cs signal is brought low. execution of a read instruction is independent of wds instruction. refer write disable cycle diagram. protect register instructions following five instructions, prread, pren, prclear, prwrite and prds are specific to operations intended for protect register. the pre pin should be held high during these instructions. 1) protect register read (prread) this instruction reads the content of the internal protect register. content of this register is 6-bit wide and is the starting address of the write-protected section of the memory array. all memory locations greater than or equal to this address are write-protected. input information (start bit, opcode and address) for this prread instruction should be issued as listed under table1. upon receiv- ing a valid input information, decoding of the opcode and the address is made, followed by data transfer (address information) from the protect register. this 6-bit data is then shifted out on the do pin with the msb first and the lsb last. like the read instruction a dummy-bit (logical 0) precedes this 6-bit data output string. output data changes are initiated on the rising edge of the sk clock. after reading the 6-bit data, the cs signal can be brought low to end the prread cycle. the pre pin should be held high during this cycle. refer protect register read cycle diagram. 2) protect register enable (pren) this instruction is required to enable prclear, prwrite and prds instructions and should be executed prior to executing prclear, prwrite and prds instructions. however, this pren instruction is enabled (valid) only the following are true device is write-enabled (refer wen instruction) pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this pren instruction should be issued as listed under table1. the protect register becomes enabled for prclear, prwrite and prds instructions at the end of this cycle when the cs signal is brought low. note that this pren instruction must immediately precede a prclear, prwrite or prds instruction. in other words, no other instruction should be executed between a pren instruction and a prclear, prwrite or prds instruction. refer protect register enable cycle diagram. 3) protect register clear (prclear) this instruction clears the content of the protect register and therefore enables write operations (write or wrall) to all memory locations. executing this instruction will program the content of the protect register with a pattern of all 1s. however, in this case, write operation to the last memory address (0x111111) is still enabled. prclear instruction is enabled (valid) only when the following are true: pren instruction was executed immediately prior to prclear instruction pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this prclear instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed clear cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal clear cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer protect register clear cycle diagram. 4) protect register write (prwrite) this instruction is used to write the starting address of the memory section to be write-protected into the protect register. after the execution of prwrite instruction, all memory locations greater than or equal to this address are write-protected. prwrite instruction is enabled (valid) only the following are true: prclear instruction was executed first (to clear the protect register) pren instruction was executed immediately prior to prwrite instruction pe pin is held high during this cycle pre pin is held high during this cycle input information (start bit, opcode and address) for this prwrite instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. refer protect register write cycle diagram. 5) protect register disable (prds) unlike all other instructions, this instruction is a one-time-only instruction which when executed permanently write-protects the protect register and renders it unalterable in the future. this instruction is useful to safeguard vital data (typically read only data) in the memory against any possible corruption. prds instruction is enabled (valid) only the following are true: pren instruction was executed immediately prior to prds instruction pe pin is held high during this cycle pre pin is held high during this cycle
8 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read input information (start bit, opcode and address) for this prds instruction should be issued as listed under table1. after inputting the last bit of address (a0 bit), cs signal must be brought low before the next rising edge of the sk clock. this falling edge of the cs initiates the self-timed programming cycle. it takes t wp time (refer appropriate dc and ac electrical characteristics table) for the internal programming cycle to finish. during this time, the device remains busy and is not ready for another instruction. status of the internal programming can be polled as described under write instruction description. while the device is busy, it is recommended that no new instruction be issued. the protect register is permanently write-protected at the end of this cycle. refer protect register disable cycle diagram. clearing of ready/busy status when programming is in progress, the data-out pin will display the programming status as either busy (low) or ready (high) when cs is brought high (do output will be tri-stated when cs is low). to restate, during programming, the cs pin may be brought high and low any number of times to view the programming status without affecting the programming operation. once programming is completed (output in ready state), the output is cleared (returned to normal tri-state condition) by clocking in a start bit. after the start bit is clocked in, the output will return to a tri-stated condition. when clocked in, this start bit can be the first bit in a command string, or cs can be brought low again to reset all internal circuits. refer clearing ready status diagram. related document application note: an758 - using fairchild s microwire ee- prom.
9 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read t css synchronous data timing cs sk pre pe di do (data read) do (status read) valid status t pres t pes t dis t dih t pd t dh t sv t skh t skl t csh t preh t peh t df t df t pd valid input valid input valid output valid output cs sk di do high - z dummy bit 1 1 0 a5 a4 a1 a0 pre 0 d15 d1 d0 t cs normal read cycle (read) address bits(6) start bit opcode bits(2) 93cs46: address bits pattern -> user defined pe timing diagrams cs sk di do high - z dummy bit data(n) 1 1 0 a5 a0 pre 0 d15 d0 d15 d0 d15 d0 t cs sequential read cycle (pre = 0; pe = x) data(n+1) data(n+2) address bits(6) start bit opcode bits(2) 93cs46: address bits pattern -> user defined
10 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read timing diagrams (continued) address bits(6) cs pe sk di do high - z write disable cycle (wds) start bit 93cs46: address bits pattern -> 0-0-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a5 a4 a1 a0 pre t cs address bits(6) data bits(16) cs pe sk di do high - z t cs write cycle (write) start bit 93cs46: address bits pattern -> user defined data bits pattern -> user defined opcode bits(2) 1 0 1 a5 a4 a1 a0 d15 d14 d1 d0 pre busy ready t wp address bits(6) cs pe sk di do high - z write enable cycle (wen) start bit 93cs46: address bits pattern -> 1-1-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a5 a4 a1 a0 pre t cs
11 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read timing diagrams (continued) cs sk di do high - z dummy bit 1 1 0 a5 a4 a1 a0 pre pe 0 d5 d1 d0 t cs protect register read cycle (prread) address bits(6) start bit opcode bits(2) 93cs46: address bits pattern -> x-x-x-x-x-x; (x -> don't care, can be 0 or 1) address bits(6) cs pe sk di do high - z protect register enable cycle (pren) start bit 93cs46: address bits pattern -> 1-1-x-x-x-x; (x -> don't care, can be 0 or 1) opcode bits(2) 1 0 0 a5 a4 a1 a0 pre t cs address bits(6) data bits(16) cs pe sk di do high - z t cs write all cycle (wrall) start bit 93cs46: address bits pattern -> 0-1-x-x-x-x; (x -> don't care, can be 0 or 1) data bits pattern -> user defined opcode bits(2) 1 0 0 a5 a4 a1 a0 d15 d14 d1 d0 pre busy ready t wp
12 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read timing diagrams (continued) address bits(6) cs pe sk di do high - z t cs protect register write cycle (prwrite) start bit 93cs46: address bits pattern -> user defined opcode bits(2) 1 0 1 a5 a4 a1 a0 pre busy ready t wp address bits(6) cs pe sk di do high - z t cs protect register disable cycle (prds) start bit 93cs46: address bits pattern -> 0-0-0-0-0-0 opcode bits(2) 1 0 0 a5 a4 a1 a0 pre busy ready t wp address bits(6) cs pe sk di do high - z t cs protect register clear cycle (prclear) start bit 93cs46: address bits pattern -> 1-1-1-1-1-1 opcode bits(2) 1 1 1 a5 a4 a1 a0 pre busy ready t wp
13 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read timing diagrams (continued) cs pe sk di do high - z high - z clearing ready status start bit note: this start bit can also be part of a next instruction. hence the cycle can be continued(instead of getting terminated, as shown) as if a new instruction is being issued. pre busy ready
14 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read molded package, small outline, 0.15 wide, 8-lead (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.004 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45
15 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read 8-pin molded tssop, jedec (mt8) package number mtc08 physical dimensions inches (millimeters) unless otherwise noted 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0118 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
16 www.fairchildsemi.com fm93cs46 rev. c.1 fm93cs46 (microwire bus interface) 1024-bit serial eeprom with data protect and sequential read physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841

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